'386 Opcode Summary Preparations for a 32-bit assembler for Unix/Linux/etc. Irrelevant instructions left out.. e.g., segmentation & supervisor-mode opcodes. Abbreviations: word = 32 bits (16 bits in real mode) disp = displacement (address.. absolute for data, relative for code) short = byte relative near = word relative imm = immediate value reg = general register r/m = register/memory (as indicated by encodings below) xrm = "mod reg r/m" byte, followed by displacement depending on xm +w = bit 0 = word size (0=byte, 1=word) +d = bit 1 = direction (reverse src,dest) Applies to MOV, ALU +s = bit 1 = sign-extend imm8 to word Applies to PUSH, ALU, IMUL3 Register Encoding: 0 1 2 3 4 5 6 7 byte AL CL DL BL AH CH DH BH word AX CX DX BX SP BP SI DI (and EAX, etc.) sreg ES CS SS DS FS GS "xrm" Encoding: (m = reg r = other register/whatever, doesn't matter here) 0rm DS:[reg] 1rm disp8 DS:[reg + disp8] 2rm disp32 DS:[reg + disp32] 3rm reg (NO EXCEPTIONS) Exceptions: (for x=0,1,2 only) 0r5 disp32 DS:[disp32] xr5 SS: default for EBP xr4 sib As follows: "sib" Encoding: (Scale*Index+Base) 0r4 sib DS:[base + scale*index] 1r4 sib disp8 DS:[base + scale*index + disp8] 2r4 sib disp32 DS:[base + scale*index + disp32] Exceptions: 0r4 si5 disp32 DS:[scale*index + disp32] r=4,5 SS: default for ESP, EBP xr4 04b No Index (scale must be 0) xr4 s4b (s>0) Undefined! MOV 210+dw xrm MOV r/m, reg 214+d xsm MOV r/m, sreg (not used in Unix programs) 240+dw disp MOV acc, mem 26r+(8w) imm MOV reg, imm (26r if byte, 27r if word-size) 306+w xrm imm MOV r/m, imm LEA 215 xrm LEA reg, r/m XCHG 206+w xrm XCHG reg, r/m 22r XCHG EAX, reg (XCHG EAX,EAX = NOP) TEST 204+w xrm TEST reg, r/m 250+w imm TEST acc, imm 366+w x0m imm TEST r/m, imm ALU 0p0+dw xrm ADD r/m, reg 0p4+w imm ADD acc, imm 200+sw xpm imm ADD r/m, imm (there is no 202: "extend word->byte") p=0 ADD 1 OR 2 ADC 3 SBB 4 AND 5 SUB 6 XOR 7 CMP 366+w x2m NOT r/m 366+w x3m NEG r/m 366+w x4m MUL r/m 366+w x5m IMUL r/m 366+w x6m DIV r/m 366+w x7m IDIV r/m 017 257 xrm imm IMUL reg, r/m 151+(2w) xrm imm IMUL reg, r/m, imm (r/m * imm -> reg) INC/DEC 10r INC reg32 11r DEC reg32 376+w x0m INC r/m 376+w x1m DEC r/m SHIFT & ROTATE 300+w xpm imm8 ROL r/m, imm 320+w xpm ROL r/m, 1 322+w xpm ROL r/m, CL p=0 ROL p=1 ROR p=2 RCL p=3 RCR p=4 SHL/SAL p=5 SHR p=7 SAR BCD CONVERSION 047 DAA 057 DAS 067 AAA 077 AAS 324 012 AAM (012 = base 10. Some 80x86 chips accept others.) 325 012 AAD ZERO/SIGN EXTEND 017 266+w MOVZX reg, r/m8 (extend byte to full width) 017 276+w MOVSX reg, r/m8 230 CBW / CWDE (zero-extend byte to full width) 231 CWD / CDQ CONTROL TRANSFER 160+cc disp8 Jcc (short) 017 200+cc disp32 Jcc (near) 017 220+cc x0m SETcc r/m8 340 disp8 LOOPNE 341 disp8 LOOPE 342 disp8 LOOP 343 disp8 JCXZ 350 disp CALL disp (relative address) 351 disp JMP disp 303 RET 302 imm16 RET imm (drop locals from stack) 310 imm32 imm8 ENTER locals, nesting 311 LEAVE 313 RET FAR (pops CS:IP) 312 imm16 RET FAR imm PUSH/POP 12r PUSH reg32 (like INC/DEC reg32) 13r POP reg32 150+s imm PUSH imm 377 x6m PUSH r/m 217 x0m POP r/m 140 PUSHA 141 POPA STRING 244+w MOVS 246+w CMPS 252+w STOS 254+w LODS 256+w SCAS 154+w INS (acc, DX assumed) 156+w OUTS (DX, acc assumed) IN/OUT 344+w imm8 IN acc, port 346+w imm8 OUT port, acc 354+w IN acc, DX 356+w OUT DX, acc FLAGS 234 PUSHF 235 POPF 236 SAHF 237 LAHF 365 CMC 370 CLC 371 STC 372 CLI 373 STI 374 CLD 375 STD MISCELLANEOUS 017 31r BSWAP reg 364 HLT 315 imm8 INT imm8 316 INT0 314 INT3 317 IRET 360 LOCK 220 NOP 233 WAIT 327 XLAT (AL = [EBX+AL])